The present invention relates to the field of voltage translator circuits, and more particularly to voltage translators within matrix drive integrated circuits.
Voltage translators are typically employed to convert logic level drive control signals into output signals suitable for driving a load. Often, the output drive signal exceeds the voltage level of the logical control signal. In this case, the voltage translator acts as a voltage amplifier or isolator. A voltage translator for digital logical control signals should have low average and peak power dissipation, small cell size, fast load switching, and possibly with controlled output slew rate (to avoid generation of electromagnetic interference and switching transients).
A typical voltage translator circuit provides a four transistor cell having two pull down NMOS transistors, referenced to a common ground, which are complementarily driven by a logic control signal and an inverter, respectively, and two pull up PMOS transistors, referenced to a medium voltage, typically higher than the logic power supply reference voltage, which are xe2x80x9ccross coupledxe2x80x9d to provide positive feedback. A complementary output is produced at the respective nodes between the PMOS and NMOS transistors.
In alternate known designs, the PMOS transistor is replaced with a resistive structure, providing a continuous quiescent current draw during the full pulse period. Alternately, for heavy loads, the high and low side logic may be separately controlled. Such designs, however, are typically unsuitable for modern high density integrated circuits which contain many voltage translators which switch essentially in synchronism.
One of the known advantages of reflective active matrix projection display devices with liquid crystal on silicon is that the drivers can be integrated with the active matrix itself. This allows improved performance and reliability, with lowered total system cost.
In one type of design, an analog reference ramp digital-to-analog converter (D/A) scheme is used to convert digital logic-level incoming data signals 1 into analog column voltages on the panel. A global analog ramp 3 signal is generated every row period 7. Each column tracks the global analog ramp signal, until it reaches its intended gray scale. At that time, it is controlled to stop tracking, and holds its voltage till the end of the row period. The digital data for each respective individual column are converted into simultaneous, pulse width modulated signals. The pulse width modulated signals control the analog track-and-hold switches 4 between respective columns and the global analog ramp 3 signal. In this way the digital video data are converted into analog voltages on the columns. This arrangement is shown in FIG. 1.
As shown in FIG. 1, column data 1 is received by logic circuit 2, to control the modulation of the liquid crystal display (LCD) pixels 8. A global analog ramp 3 is generated in each row period 7, which is selectively latched by track and hold switches 4, based on an individual pulse width timing generated by the logic circuit 2. The latched analog ramp voltage on each column 5 is used to drive the corresponding liquid crystal display pixel of the selected row. At the end of each row period 7, an end of row select signal 6 resets the track and hold switches 4, preparing for driving the next row.
FIG. 2 shows a prior art voltage translator circuit system. A tracking signal 10 is received for each column, from the logic circuit 2. A buffer 16 and inverter 17 (or pair of inverters) buffer the signal and generate a complementary pair, for driving the voltage translator 12 itself. The voltage translator converts the standard logic 11 voltage levels to a medium voltage level, generated by the medium voltage power supply 14. The voltage translator 12 has two complementary branches, each having an NMOS transistor 18, 19, for active pull down, and a PMOS transistor 20, 21, for active pull up, in series. Each PMOS transistor 20, 21 is driven with positive feedback from the node between the NMOS and PMOS transistor of the complementary branch. These same nodes are used here to drive an analog transmission gate 13 including an NMOS transistor 22 and PMOS transistor 23, to control the track and hold of the global analog ramp signal 15, which drives each column. The logic to generate the pulse width modulated signals for each column is standard low voltage, e.g., 5V or less, but each track and hold switch has to handle the analog voltage range for the columns, which is generally larger than the standard logic voltage swing, e.g., 5V peak or more power supply voltage, typically 12 V min. A voltage translator circuit is provided for each column to convert the logical control signal into the potentially higher voltage drive signal. The voltage translator circuit therefore translates a complementary signal pair at standard logic voltages into a medium voltage signal pair. A known voltage translator circuit is shown in FIG. 2. Such a voltage translator circuit is disclosed in U.S. Pat. No. 5,723,986 and U.S. Pat. No. 5,682,174, expressly incorporated herein by reference, and JP 07-168,153 (Apr. 7, 1995). See, also U.S. Pat. No. 5,473,268, expressly incorporated herein by reference.
The track and hold switch is shown as a transmission gate 13 in FIG. 2, but other implementations are also possible. The known voltage translator 12 shown in FIG. 2 uses internal positive feedback to switch. Whenever the complementary inputs switch, one branch is temporarily floating (both the bottom NMOS transistor and the top PMOS transistor are xe2x80x9cOffxe2x80x9d), while the other branch draws heavy current (both NMOS and PMOS transistor are xe2x80x9cOnxe2x80x9d). When the active NMOS transistor pulls the gate of the passive PMOS over the threshold voltage, it starts conducting and positive feedback occurs to complete the switch event. The gate of each NMOS transistor (18,19) is driven with logic voltage levels, and yet has to compete with the PMOS transistor that has essentially the full medium voltage power supply 14 voltage swing on its gate. Therefore, the NMOS transistors have to be substantially larger than the PMOS transistors (20,21), in order to pull the junction node voltage to a low enough level to turn the PMOS transistor in the other branch xe2x80x9cOnxe2x80x9d.
The present invention provides an improved voltage translator circuit which includes an additional pair of PMOS transistors interposed between the xe2x80x9ccross coupledxe2x80x9d pull up PMOS transistors and the output drive power supply (medium voltage). The drive voltage for these additional PMOS transistors is generated globally for an array of voltage translators, and is referenced to the output drive power supply (medium voltage).
By adding additional controls to the voltage translators of the known four transistor voltage translator design, performance can be improved. The additional controls are used to prepare the translator for an imminent switching event. This is possible because the switching events are sufficiently predictable within a row period. Thus, a switching transient is suppressed by blocking the current through the NMOS transistor immediately prior to the switching event, by turning xe2x80x9cOffxe2x80x9d the additional PMOS transistor. Since the circuit is complementary controlled, it is not necessary to provide active control to both branches of the circuit. Thus, the additional PMOS transistor in the non-actively controlled branch of the circuit can be held in a partially conducting condition continuously, in order to limit current flow during switching. The additional series PMOS transistors also allow the switching performance to be improved. FIG. 3 shows the arrangement according to the present invention.
In operation, the voltage translator circuit according to the present invention prepares for the switching event by turning xe2x80x9cOffxe2x80x9d the series PMOS transistor in the branch that would otherwise be drawing heavy current. The series PMOS transistor in the complementary branch should be turned xe2x80x9cOnxe2x80x9d at this time, to provide appropriate positive feedback for switching.
The result is not only a reduced current spike on the power supply, but also reduced overall current consumption, because the current in the first branch is blocked. Switching performance is improved, because the NMOS transistor in the first branch no longer has to compete with the PMOS transistor in the same branch. This means that the NMOS transistor size can be substantially reduced, while maintaining improved switching performance. Therefore, the total circuit area can be even smaller than the known circuit. The improved switching performance also tends to improve the balance between the complementary outputs. This is important when driving transmission gates and/or other charge compensating track and hold switches.
While additional control signals are required for each voltage translator cell, therefore increasing drive circuit xe2x80x9coverheadxe2x80x9d, in a display application, the additional overhead can be very low, because the column switches are modulated in a known sequence. For example, in the above-described analog reference D/A scheme shown in FIG. 1, all columns start tracking at the same time. Each column driver circuit stops tracking at a time that corresponds to the individual gray scale for that column. Therefore the extra control inputs for all columns can be driven in parallel from a pair of global signals. The active control inputs 30 for the switched branch go high just before the columns start tracking and low afterwards. The static control inputs 33 are DC driven such that the PMOS transistor acts as a permanent current limiter. The net result is that at the start of tracking, the actively controlled PMOS transistor is turned xe2x80x9cOffxe2x80x9d, and the transition is rather slow because of the current limiting of the passive controlled PMOS transistor. This slowed response, however, doesn""t affect sampling accuracy in this scheme, and in fact tends to limit the otherwise massive transient which occurs when all columns suddenly settle to the current analog ramp voltage.
It is noted that the 2V reference voltage driving the gate of the passively controlled PMOS transistor is but one option. This PMOS transistor may also be controlled, for example, by a global current mirror, a global active control signal, or intrinsically by providing the PMOS device with a very small width to length ratio with the gate tied to the substrate. It is therefore understood that this PMOS device serves primarily as a current limiter, which should be operative as such especially during transitions, and may remain in this condition throughout the operation cycle. FIG. 6 shows an implementation where the current limiting function of the passively controlled transistor is created by designing the active PMOS transistor of that branch with a small width to length ratio. FIG. 7 shows that the current limiting function can also be obtained with the extra PMOS devices in series between original PMOS devices and cross-coupled node.
After the start of tracking, the actively controlled PMOS transistor is turned xe2x80x9cOnxe2x80x9d again, in preparation for the actual transition to the hold state of the column. The latter transition is critical for sampling accuracy, and in this case the weak conduction of the passively controlled PMOS transistor and the good conduction of the actively controlled PMOS transistor help in making the switch very fast.
Alternate schemes are also possible. In displays with a traditional-type shift register oriented column control, the inputs to the additional series PMOS transistors may be derived from the translator of the previous column circuit in the shift chain, as shown in FIG. 5.
Alternately, the control signals for the additional series PMOS transistors can be generated locally as a phase delayed signal of the output of their respective branches. Such a phase delay, for example, could be generated by series resistors and possibly additional parallel gate capacitors, as shown in FIG. 4.
It is noted that, while the present voltage translator circuit has been described with respect to standard complementary metal oxide silicon (CMOS) semiconductor processes, the same principles may also be applied to atypical processes and atypical semiconductors. For example, gallium arsenide, silicon-germanium, silicon carbide, organic substrate, and other semiconductor materials may be employed. The semiconductor may be crystalline, amorphous, thin film, semiconductor on insulator or other known type. The invention may also be adapted for enhancement or depletion mode semiconductors. Therefore, it is apparent that the invention is not limited to the preferred embodiment.